In general, a digital/analog converter circuit comprises a current output type digital/analog converter and a current/voltage converter. FIG. 2A shows a prior art general relation of connection of a digital/analog converter circuit comprising a current output type digital/analog converter 2 and a current/voltage converter 21 connected to a next stage of the digital/analog converter 2. The digital/analog converter 2 receives a 16 bit serial digital signal S.sub.1, converts the digital signal S.sub.1 into a parallel signal by a signal processing portion 19 involved therein and supplies in parallel with a predetermined period T to bit current output portions 3 through 18, bit signals S.sub.2 to S.sub.17 corresponding to respective values between MSB (Most Significant Bit) and LSB (Least Significant Bit) and inversion bit signals S.sub.2 to S.sub.17 which are inversions of the bit signals S.sub.2 to S.sub.17, respectively.
As noted from FIG. 2B, the bit current output portion 3 comprises a circuit which includes a transistor Q1 having a base connected to an input terminal 3.sub.1 and a collector connected to a base of a transistor Q3 and also connected through a resistor R4 to a positive electric source Vc and a transistor Q2 having a base connected to an input terminal 3.sub.2 and a collector connected to the positive electric source Vc while emitters of the transistors Q1 and Q2 are connected commonly to a constant current source 20.
The transistor Q3 has a collector connected to the positive electric source Vc while a transistor Q4 has a collector and a base connected commonly to an output terminal 3.sub.3. The emitters of the transistors Q3 and Q4 are connected commonly to collectors of transistors Q5 and Q6. A reference voltage Vr is applied to a base of the transistor Q5, a base of the transistor Q6 is connected to an emitter of the transistor Q5 while an emitter of the transistor Q6 is connected to a bit current source 3.sub.4.
Although the other bit current output portions 4 through 18 may be constructed in the same manner as the bit current output portion 3, the respective constant current values of bit current sources 3.sub.4 through 18.sub.4 (not shown) of the bit current output portions 4 through 18 are set at two times the constant current value of the immediately lower bit current source. More particularly, a relation of the value of the constant current I.sub.1 of the bit current source 3.sub.4 of the MSB and the value of the constant current I.sub.16 of the bit current source 18.sub.4 of the LSB is expressed by: EQU I.sub.16 =I.sub.1 /2.sup.16
An operation of the digital/analog converter 2 will be described with reference to FIG. 3.
The bit signal S.sub.2 and the inversion bit signal S.sub.2 of the MSB supplied to the input terminals 3.sub.1 and 3.sub.2 are so set as to be at the states of "H" and "L", respectively when the value of the MSB is 1. Thus, as shown in FIG. 3(a), as the states of the bit signal S.sub.2 and the inversion bit signal S.sub.2 vary in accordance with the values of the MSB, the transistors Q1 and Q2 are alternately turned on and off and a base voltage V.sub.1 of the transistor Q3 varies between the values Vh and Vl in accordance with the alternate conduction of the transistors Q1 and Q2. The values Vh and Vl of the base voltage are determined by the value of current If, the set value of the resistor R4 and the set switching areas of the transistors Q1 and Q2. For example, it is supposed that the absolute values of Vh and Vl are set to be equal to each other so that the medium level between them becomes OV.
It is further supposed that the base voltage V.sub.1 of the transistor Q3 has a wave varying as shown in FIG. 3(a) so that a velocity of variation in level is damped by the function of the capacity components of the transistors Q1 and Q2 and the resistor R4.
The base voltage Vm of the transistor Q4 which is the voltage at the output terminal 3.sub.3 of the bit current output portion 3 is set by the current/voltage converter 21 connected to the next stage thereof and in this case, it is OV because OV is applied to a non-inversion terminal of an operational amplifier 21.sub.1 as shown in FIG. 2A.
Thus, in case that the base voltage V.sub.1 of the transistor Q3 is more than the base voltage Vm of the transistor Q4, then the constant current I.sub.1 through the bit current source 3.sub.4 flows through the emitter of the transistor Q3. In case that the base voltage V.sub.1 of the transistor Q3 is less than the base voltage Vm of the transistor Q4, then it flows through the emitter of the transistor Q4. The bit current Ib.sub.1 of the MSB flowing through the output terminal 3.sub.3 is shown in FIG. 3(a). Since a variation in the state of the bit current Ib.sub.1 is always delayed by a constant delay time t relative to a variation in the bit signal S.sub.2, there occurs no inconvenience due to its delay time t.
Although only the bit current Ib.sub.1 through the bit current output portion 3 varying in accordance with the values of the MSB is described, the bit currents Ib.sub.2 through Ib.sub.16 of the 2SB through the LSB flow through the corresponding bit current output portions with a predetermined relation of current varying in accordance with the values of the respective bits in the same manner as the bit current Ib.sub.1.
The current/voltage converter 21 supplies an output voltage signal Vo having a voltage value varying in proportion to a value of an addition current Io of the respective bit currents Ib.sub.1 through Ib.sub.16 through a low-pass filter 22 and a coupling capacitor C1 to an output portion 23.
The low-pass filter 22 serves to cut the frequency component of period less than a half of the aforementioned period T in an acute attenuation characteristic while the coupling capacitor C1 serves to cut a direct voltage component.
The transistors Q5 and Q6 darlington-connected to each other serve to make constant the voltage applied to the bit current source 3.sub.4.
As noted from the foregoing, the analog voltage signal corresponding to the input 16 bit serial digital signal S.sub.1 is output from the output portion 23 by the digital/analog converter 2, the current/voltage converter 21, the low-pass filter 22 and the coupling capacitor C1.
As shown in FIG. 3(a), the base voltage V.sub.1 of the transistor Q3 responds in a damped manner to level variation by the function of the capacitance component of the transistor Q1 and the resistor R4 connected to the collector thereof. The respective bit currents Ib rapidly vary in their state because of rapid switching operation of a current flowing path by the transistors Q3 and Q4 which constitute a sort of diode switch.
In case that the set voltages Vh and Vl are constantly offset in a positive or plus direction by various conditions such as manufacturing errors so that they become Vh.sub.1 and Vl.sub.1, respectively as shown in FIG. 3(b), the base voltage Vm of the transistor Q4 is so set to be OV and as a result, the delay rise time t.sub.1 of the bit current Ib.sub.1 is different from the delay fall time t.sub.2 of the bit current Ib.sub.1. Thus, the following relation of the delay times t.sub.1, t.sub.2 and t will be established; EQU t.sub.1 &gt;t&gt;t.sub.2
On the other hand, in case that the set voltages Vh and Vl are offset in a negative or minus direction, the following relation of the delay times t.sub.1, t.sub.2 and t will be established; EQU t.sub.1 &lt;t&lt;t.sub.2
Since a variation in the delay times t.sub.1 and t.sub.2 is generated not only for the bit current Ib.sub.1, but also for the bit currents Ib.sub.2 through Ib.sub.16 of the 2SB through the LSB, so that timing of turning on and off the diode switch is different from each other. Therefore, there occurs a glitch, which causes the converted analog signal to have harmonic distortion.